//=========================================================================
//
//                  S Y N C M O S   T E C H N O L O G Y
//
//           COPYRIGHT (c)   2008 BY SyncMOS Technologies International,Inc.
//                     --  ALL RIGHTS RESERVED  --
//
// File Name : SM59D04G2SFR.H
// Created: 2008/05/26
// Author: Chia Tsai
// Description:
//	This header file is define SyncMOS's SM59D04G2 SFR.
// Revision: 0.1
// History:
//=========================================================================
#ifndef __SM59D04G2SFR_H__
#define __SM59D04G2SFR_H__

/*  BYTE Registers  */
sfr P0    		= 0x80;			// Port 0
sfr SP    		= 0x81;			// Stack pointer
sfr DPL   		= 0x82;			// Data Pointer 0 Low byte
sfr DPH   		= 0x83;			// Data Pointer 0 High byte
sfr DPL1		= 0x84;			// Data Pointer 1 Low byte
sfr DPH1		= 0x85;			// Data Pointer 1 High byte
sfr DPS   		= 0x86;			// Data Pointer select register
sfr PCON  		= 0x87;			// Power Control
sfr TCON  		= 0x88;			// Timer/Counter Control
sfr TMOD  		= 0x89;			// Timer Mode Control
sfr TL0   		= 0x8A;			// Timer 0 Low byte
sfr TL1   		= 0x8B;			// Timer 1 Low byte
sfr TH0   		= 0x8C;			// Timer 0 High byte
sfr TH1   		= 0x8D;			// Timer 1 High byte
sfr WDTC		= 0x8E;			// Watchdog control register
sfr	WDTK		= 0x8F;			// Watchdog clear key register
sfr P1    		= 0x90;			// Port 1
sfr	CC2DH		= 0x91;			// Compare/Capture 2 data register (High byte)
sfr	CC2DL		= 0x92;			// Compare/Capture 2 data register (Low byte)
sfr	CC3DH		= 0x93;			// Compare/Capture 3 data register (High byte)
sfr	CC3DL		= 0x94;			// Compare/Capture 3 data register (Low byte)
sfr	CC4DH		= 0x95;			// Compare/Capture 4 data register (High byte)
sfr	CC4DL		= 0x96;			// Compare/Capture 4 data register (Low byte)
sfr SCON 		= 0x98;			// Serial Port control register
sfr SBUF 		= 0x99;			// Serial Port Data Buffer
sfr PCACH     	= 0x9A;			// PCA counter high byte
sfr PCACL		= 0x9B;			// PCA counter low byte
sfr	CC0DH		= 0x9C;			// Compare/Capture 0 data register (High byte)
sfr	CC0DL		= 0x9D;			// Compare/Capture 0 data register (Low byte)
sfr	CC1DH		= 0x9E;			// Compare/Capture 1 data register (High byte)
sfr	CC1DL		= 0x9F;			// Compare/Capture 1 data register (Low byte)
sfr P2    		= 0xA0;			// Port 2
sfr	PCAC1		= 0xA1;			// PCA control register 1
sfr PCAC2     	= 0xA2;			// PCA control register 2
sfr CC0CON		= 0xA3;			// Compare/Capture 0 control register
sfr CC1CON		= 0xA4;			// Compare/Capture 1 control register
sfr CC2CON		= 0xA5;			// Compare/Capture 2 control register
sfr CC3CON		= 0xA6;			// Compare/Capture 3 control register
sfr CC4CON		= 0xA7;			// Compare/Capture 4 control register
sfr IER  		= 0xA8;			// Interrupt Enable register
//sfr IE  		= 0xA8;			// Interrupt Enable register
sfr IER1		= 0xA9;			// Interrupt Enable register 1
sfr P3    		= 0xB0;			// Port 3
sfr IP     		= 0xB8;			// Interrupt Priority register
sfr IP1			= 0xB9;			// Interrupt Priority register 1
sfr SCONF		= 0xBF;			// System control flag
sfr T2CON		= 0xC8;			// Timer 2 control register
sfr T2MOD		= 0xC9;			// Timer 2 mode
sfr	RCAP2L		= 0xCA;			// Reload/Capture data low byte
sfr	RCAP2H		= 0xCB;			// Reload/Capture data high byte
sfr TL2			= 0xCC;			// Timer 2 Low byte
sfr TH2			= 0xCD;			// Timer 2 High byte
sfr PSW  		= 0xD0;			// Program Status Word
sfr	P4			= 0xD8;			// Port 4
sfr ACC  	 	= 0xE0;			// Accumulator
sfr B     		= 0xF0;			// B register
sfr	ISPFAH		= 0xF4;			// ISP Flash address high byte
sfr	ISPFAL		= 0xF5;			// ISP Flash address low byte
sfr	ISPFD		= 0xF6;			// ISP Flash data register
sfr	ISPC		= 0xF7;			// ISP Control register
sfr	KBLS		= 0xFD;			// Keyboard level selector register
sfr KBE			= 0xFE;			// Keyboard input enable register
sfr KBF			= 0xFF;			// Keyboard flag register

/* replace STC*/

sfr	AUXR = 0XBF;
sfr AUXR1 = 0x86;

/*  BIT Registers  */
/* Port 0 */
sbit P00		= P0 ^ 0;
sbit P01		= P0 ^ 1;
sbit P02		= P0 ^ 2;
sbit P03		= P0 ^ 3;
sbit P04		= P0 ^ 4;
sbit P05		= P0 ^ 5;
sbit P06		= P0 ^ 6;
sbit P07		= P0 ^ 7;

/* Port 1 */
sbit P10		= P1 ^ 0;
sbit P11		= P1 ^ 1;
sbit P12		= P1 ^ 2;
sbit P13		= P1 ^ 3;
sbit P14		= P1 ^ 4;
sbit P15		= P1 ^ 5;
sbit P16		= P1 ^ 6;
sbit P17		= P1 ^ 7;

/* Port 2 */
sbit P20		= P2 ^ 0;
sbit P21		= P2 ^ 1;
sbit P22		= P2 ^ 2;
sbit P23		= P2 ^ 3;
sbit P24		= P2 ^ 4;
sbit P25		= P2 ^ 5;
sbit P26		= P2 ^ 6;
sbit P27		= P2 ^ 7;

/* Port 3 */
sbit P30		= P3 ^ 0;
sbit P31		= P3 ^ 1;
sbit P32		= P3 ^ 2;
sbit P33		= P3 ^ 3;
sbit P34		= P3 ^ 4;
sbit P35		= P3 ^ 5;
sbit P36		= P3 ^ 6;
sbit P37		= P3 ^ 7;

/* Port 4 */
sbit P40		= P4 ^ 0;
sbit P41		= P4 ^ 1;
sbit P42		= P4 ^ 2;
sbit P43		= P4 ^ 3;

/*  TCON  */
sbit TF1  		= TCON ^ 7;
sbit TR1  		= TCON ^ 6;
sbit TF0  		= TCON ^ 5;
sbit TR0  		= TCON ^ 4;
sbit IE1  		= TCON ^ 3;
sbit IT1  		= TCON ^ 2;
sbit IE0  		= TCON ^ 1;
sbit IT0  		= TCON ^ 0;

/*  SCON */
sbit SM0  		= SCON ^ 7;
sbit SM1  		= SCON ^ 6;
sbit SM2 		= SCON ^ 5;
sbit REN 		= SCON ^ 4;
sbit TB8 		= SCON ^ 3;
sbit RB8	 	= SCON ^ 2;
sbit TI  		= SCON ^ 1;
sbit RI  		= SCON ^ 0;

/*  IER  */
sbit EA   		= IER ^ 7;
sbit ET2  		= IER ^ 5;
sbit ES  			= IER ^ 4;
sbit ET1  		= IER ^ 3;
sbit EX1  		= IER ^ 2;
sbit ET0  		= IER ^ 1;
sbit EX0  		= IER ^ 0;

/*  IP  */
sbit PT2  		= IP ^ 5;
sbit PS  		= IP ^ 4;
sbit PT1  		= IP ^ 3;
sbit PX1  		= IP ^ 2;
sbit PT0  		= IP ^ 1;
sbit PX0  		= IP ^ 0;

/*  T2CON */
sbit TF2 		= T2CON ^ 7;
sbit EXF2 		= T2CON ^ 6;
sbit RCLK 		= T2CON ^ 5;
sbit TCLK 		= T2CON ^ 4;
sbit EXEN2 		= T2CON ^ 3;
sbit TR2 		= T2CON ^ 2;
sbit CT2		= T2CON ^ 1;
sbit CPRL2		= T2CON ^ 0;

/*  PSW  */
sbit CY   		= PSW ^ 7;
sbit AC   		= PSW ^ 6;
sbit F0   		= PSW ^ 5;
sbit RS1  		= PSW ^ 4;
sbit RS0  		= PSW ^ 3;
sbit OV 	  	= PSW ^ 2;
sbit F1			= PSW ^ 1;
sbit P    		= PSW ^ 0;

#endif

